1. M. Davies, N. Srinivasa, T. Lin, G. Chinya, Y. Cao, S.H. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain, Y. Liao, C. Lin, A. Lines, R. Liu, D. Mathaikutty, S. McCoy, A. Paul, J. Tse, G. Venkataramanan, Y. Weng, A. Wild, Y. Yang, H. Wang, Loihi: a neuromorphic manycore processor with on-chip learning. IEEE Micro 38(1), 82–99 (2018)
2. C. dos Reis Filho, E. da Silva, E. de L. Azevedo, J. Seminario, L. Dibb, Monolithic data circuit-terminating unit (DCU) for a one-wire vehicle network, in Proceedings of the 24th European Solid-State Circuits Conference (ESSCIRC ’98), Hague, Sept 1998, pp. 228–231
3. B. Fleischer et al., A scalable multi-TeraOPS deep learning processor core for AI training and inference, in Symposium on VLSI Circuits, Honolulu, June 2018
4. Freescale semiconductors, MPC860 PowerQUICC Family User’s Manual (2004). https://www.nxp.com/docs/en/reference-manual/MPC860UM.pdf
5. S.B. Furber, F. Galluppi, S. Temple, L.A. Plana, The SpiNNaker project. Proc. IEEE 102(5), 652–665 (2014)