1. Bell G. Bell’s law for the birth and death of computer classes. Commun. ACM, 2008, 51(1): 86–94
2. Kumar S, Hughes C J, Nguyen A. Carbon: Architectural support for fine-grained parallelism on chip multiprocessors. ISCA’07, 2007, 162–173
3. Leverich J, Arakida H, Solomatnikov A, et al. Comparing memory systems for chip multiprocessors. ISCA’07, 2007, 358–368
4. Liu C, Anand S, Kandemir M. Organizing the last line of defense before hitting the memory wall for CMPs. In: Proceedings of 10th International Symposium on High Performance Computer Architecture, 2004, 176–185
5. Kim S, Chandra D, Solihin Y. Fair cache sharing and partitioning in a chip multiprocessor architecture. In: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, 2004, 111–122