1. Choi, J., Jeon, J., & Choi, K. (2000). Power minimization of functional units by partially guarded computation. In 2000 International symposium on low power electronics and design (ISLPED’00) pp. 131–136, July.
2. Di, J., Yuan, J. S., & Hagedorn, M. (2002). Energy-aware multiplier design in multi-rail encoding logic. In The 2002 45th Midwest symposium on circuits and systems (MWSCAS-2002) (Vol. 2, pp. 294–297), Aug.
3. Hwang, W., Gristede, G. D., Sanda, P. N., Wang, S. Y., & Heidel, D. F. (1999). Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. IEEE Journal of Solid-State Circuits, 34(8), 1108–1117.
4. Hong, S., Kim, S., Papaefthymiou, M. C., & Stark, W. E. (1999). Low power parallel multiplier design for DSP applications through coefficient optimization. In 1999 twelfth annual IEEE international ASIC/SOC conference pp. 286–290, Sep.
5. Ohban, J., Moshnyaga, V. G., & Inoue, K. (2002). Multiplier energy reduction through bypassing of partial products. In 2002 Asia-Pacific conference on circuits and systems (APCCAS ’02) (Vol. 2, pp. 13–17), Oct.