Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Reference21 articles.
1. Athow, J.L., & Al-Khalili, A.J. (2008). Implementation of large-integer hardware multiplier in Xilinx FPGA. 15th IEEE international conference on electronics, circuits and systems, ICECS 2008 (pp. 1300–1303).
2. Barker, E., Barker, W., Burr, W., Polk, W., Smid, M. (2007). NIST SP800-57: Recommendation for key management Part 1: General(Revised), http://csrc.nist.gov/publications/nistpubs/800-57/sp800-57-Part1-revised2∖_Mar08-2007.pdf , NIST.
3. de Dinechin, F., & Pasca, B. (2009). Large multipliers with fewer DSP blocks (pp. 250–255). FPL.
4. Gao, S., Al-Khalili, D., Chabini, N., Langlois, P. (2010). FPGA-based efficient design approaches for large size twos complement squarers. Journal of Signal Processing Systems, 58, 3–15.
5. Gao, S., Al-Khalili, D., Chabini, N., Langlois, J.M.P. (2012). Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers & Digital Techniques, 6, 372– 383.
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