Power-effective ROM-less DDFS Design Approach with High SFDR Performance

Author:

Wang Chua-ChinORCID,Sulistiyanto Nanang,Shih Hsiang-Yu,Lin Yu-Cheng,Wang Wei

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Reference16 articles.

1. Sun, Y., Yu, X., Rhee, W., Wang, D., Wang, Z. (2010). A fast settling dual-path fractional-N PLL with hybrid-mode dynamic bandwidth control. IEEE Microwave and Wireless Components Letters, 20(8), 462–464.

2. Tierney, J., Rader, C., Gold, B. (1971). A digital frequency synthesizer. IEEE Transactions on Audio and Electroacoustics, 19(1), 48–57.

3. Pontikakis, B., Bui, H.-T., Boyer, F.-R., Savaria, Y. (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. In: IEEE MidWest Symposium on Circuits and Systems 2007 (MWSCAS ’07) (pp. 1118–1121).

4. Sotiriadis, P. (2009). Timing and spectral properties of the Flying Adder frequency synthesizers. IEEE International Frequency Control Symposium, 2009, 788–792.

5. Wang, C.-C., Hsu, C.-H., Lee, C.-C., Huang, J.-M. (2010). A ROM-less DDFS based on a parabolic polynomial interpolation method with an offset. Journal of Signal Processing Systems, 61, 1–9.

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1. Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology;Journal of Circuits, Systems and Computers;2022-04-01

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