Compact Code Generation for Tightly-Coupled Processor Arrays-Reference-Cited by-同舟云学术

Compact Code Generation for Tightly-Coupled Processor Arrays

Published:2014-05-31 Issue:1-2 Volume:77 Page:5-29
ISSN:1939-8018
Container-title:Journal of Signal Processing Systems
language:en
Short-container-title:J Sign Process Syst

Author:

Boppu Srinivas,Hannig Frank,Teich Jürgen

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Link

http://link.springer.com/content/pdf/10.1007/s11265-014-0891-2.pdf

Reference44 articles.

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2. Dutta, H., Hannig, F., Teich, J. (2006). Hierarchical partitioning for piecewise linear algorithms. In Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (PARELEC), (pp. 153–160): IEEE Computer Society.

3. Feautrier, P., & Lengauer, C. (2011). Polyhedron model In Padua, D. (Ed.), Encyclopedia of Parallel Computing, (pp. 1581–1592): Springer.

4. Fisher, J. (1983). Very long instruction word architectures and the ELI-512. In Proceedings of the 10th Annual International Symposium on Computer Architecture (ISCA), (pp. 140–150): IEEE.

5. GCC. the GNU Compiler Collection. http://gcc.gnu.org .

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